Raspberry Pi /RP2350 /PIO0 /SM2_EXECCTRL

Comparison level or IRQ index for the MOV x, STATUS instruction.

If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour.

0 (IRQ): Index 0-7 of an IRQ flag in this PIO block

8 (IRQ_PREVPIO): Index 0-7 of an IRQ flag in the next lower-numbered PIO block

16 (IRQ_NEXTPIO): Index 0-7 of an IRQ flag in the next higher-numbered PIO block

Comparison used for the MOV x, STATUS instruction.

0 (TXLEVEL): All-ones if TX FIFO level < N, otherwise all-zeroes

1 (RXLEVEL): All-ones if RX FIFO level < N, otherwise all-zeroes

2 (IRQ): All-ones if the indexed IRQ flag is raised, otherwise all-zeroes

After reaching wrap_top, execution is wrapped to this address.

After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority.

Continuously assert the most recent OUT/SET to the pins

If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

Which data bit to use for inline OUT enable

The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

If 1, side-set data is asserted to pin directions, instead of pin values

If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.